A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a MOS semiconductor device having an elevated source/drain structure and its manufacture method.
B) Description of the Related Art
High speed operation and high integration of semiconductor devices require a shortened gate length and a reduced parasitic capacitance. In order to suppress the short channel effects, it is necessary to shallow source and drain regions. In order to suppress an increase in a sheet resistance to be caused by shallow source and drain regions, techniques of forming a refractory metal silicide layer on the source and drain regions are adopted.
If the refractory metal silicide layer is formed on the shallow source and drain regions, junction leak current increases. A MOS semiconductor device has been proposed having an elevated source/drain structure which does not induce an increase in junction leak current even if a refractory metal silicide layer is formed.
A method of forming an elevated structure is known. According to this method, after impurities are implanted into source and drain regions, a semiconductor film is epitaxially grown selectively on the source and drain regions. With this method, the epitaxial growth temperature is preferably set to 600° C. or lower in order to suppress the lateral diffusion of impurities doped in the source and drain regions. Since the growth temperature cannot be made high, the growth speed of the semiconductor film is slow. This method is not suitable for mass production.
Also, heat treatment in a hydrogen atmosphere is performed before the epitaxial growth in order to remove a native oxide film formed on the surfaces of the source and drain regions. The heat treatment temperature is preferably set in a range from 700 to 900° C. in order to enhance the effects of removing the native oxide film. However, it is not preferable to set the heat treatment temperature to 600° C. or higher in order to suppress the lateral diffusion of impurities in the source and drain regions. If the heat treatment temperature is set to 600° C. or lower, the sufficient effects of removing the native oxide film cannot be expected.
If the source and drain impurity diffusion regions are formed after the elevated source/drain structure is formed, it is possible to prevent the lateral diffusion of impurities in the source and drain regions. However, if the extension regions of the lightly doped drain (LDD) structure are already formed before the elevated source/drain structure is formed, impurities in the extension regions diffuse in the lateral direction. The sufficient short channel suppression effects cannot therefore be expected.
In FIG. 12 of the publication of JP-A-2000-150886 and its related description, a manufacture method for a MOS transistor having an elevated source/drain structure is disclosed which can solve the above-described problems. According to this method, first, by using as a mask the side wall spacers covering the side walls of a gate electrode and an insulating film on the top surface of the gate electrode, an epitaxial layer is selectively grown on source and drain regions. Thereafter, impurity ions are implanted into the source and drain regions, and a titanium silicide layer is formed on the epitaxially grown layers.
After the sidewall spacers are removed, impurities are implanted to form extension regions of the LDD structure. Heat treatment is performed for 30 minutes at 950° C. to diffuse impurities and make the extension regions be continuous with the source and drain regions.
With the method disclosed in the publication of JP-2000-150886, during the heat treatment for making the extension regions be continuous with the source and drain regions, the impurities in the extension regions diffuse also toward the channel. The short channel effects become great. Further, since the heat treatment for diffusing impurities in the extension regions is preformed after the titanium silicide layer is formed, aggregation of titanium silicide is likely to occur. If there is aggregation of titanium silicide, the sheet resistance of the source and drain regions becomes high. Furthermore, with this method, the titanium silicide layer is not formed on the gate electrode. A low resistance of the gate electrode cannot therefore be expected.